The ASIC Development Process Seminar:
From Requirements to RTL to Packaged Product
Developing next-generation ASIC or SOC chips involves hundreds of critical steps. This unique one-day seminar fills in the conceptual gaps by explaining—to highly-specialized design, verification, test, and firmware engineers—just what happens during the key steps, and what issues typically arise. It covers design (RTL and on-chip analog); functional verification; placement and routing; fabrication; packaging.
Get your engineering team and support personnel ready now for the increased complexities and unexpected cross-functional interactions that are emerging with 32- and 22-nm technologies.
Hardware Description Languages
Why use up limited training budget on high-priced “experts” who can’t impedance-match to time-pressured engineers working in the trenches? Our instructors convey real-world know-how—not just the fine points of syntax—in understandable, easy-to-master lecture topics and hands-on labs.
Trying to cobble together complex data packets and busing fabric using legacy Verilog bit-vector notation? Gain familiarity with the new IEEE-1800 struct, 2-D array, and interface constructs—all fully synthesizable, and compatible with UPF.
- Verilog Refresher
Ideal for new-hires who need a fast, but comprehensive, spin-up on the in’s and out’s of Verilog syntax and techniques for synthesis and simulation. Learn to fully utilize V2K features, and avoid novice pitfalls
- VHDL for RTL Designers
This highly-focused workshop was developed to meet the urgent needs of a proficient RTL design team faced with the need to modify and debug a large VHDL IP library. Includes numerous VHDL gotcha’s.
Originally developed for a major telecom house, the one-day seminar has received outstanding reviews at sites worldwide.